Semiconductor memory device having diode cell structure

ABSTRACT

A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a non-volatile semiconductor memorydevice for storing data using a change in resistance state of a memoryelement, and particularly relates to a semiconductor memory device inwhich a memory cell is formed by connecting the memory element and adiode in series.

2. Description of Related Art

A phase change memory device using structural change of phase changematerial is known as one of non-volatile semiconductor memory devices.The phase change memory device has a structure in which a resistancevalue of a phase change element made of the phase change material ischanged by heat and thereby data can be rewritably stored. This heat isgenerated by flowing a large current in the phase change element. Whenforming a memory cell of the phase change memory device by using a MOStransistor, it is difficult to shrink the cell size in order to obtain alarge gate width capable of flowing a large write current. Therefore, aphase change memory device having a diode cell structure has beenproposed, in which a diode is used as a select switch for the phasechange element (For example, see Patent Reference 1). For example, aphase change memory device shown in FIG. 5 of the Patent Reference 1 hasa memory cell array in which a large number of memory cells having thediode cell structure are arranged in a matrix. By employing the diodecell structure, the cell size of each memory cell can be shrank, therebyachieving a high-density arrangement of the memory cells.

-   Patent Reference 1: Japanese Patent Application Laid-open No.    2007-134032

Generally, in a read operation of a memory cell having the diode cellstructure, a predetermined voltage is applied to a selected bit line,and a current flows in a selected word line through the series connectedphase change element and the diode. For example, in the phase changememory device disclosed in the Patent Reference 1, a predeterminedvoltage is applied to a bit line by a read circuit (corresponding to asense amplifier 170, a bias circuit 150, a precharge circuit 160 and aclamping circuit 140 in FIG. 5 of the Patent Reference 1) driven by aboost voltage VSA of 2.5V, and in a state where a ground potential isapplied to the word line, data stored in the phase change element can bedetermined in accordance with a change in the current flowing in thememory cell.

In order to accurately detect the change in the resistance state of thephase change element in the read operation of the phase change memorydevice having the diode cell structure, a forward voltage of the diodeneeds to be maintained constant. However, since current-voltagecharacteristics of the diode actually has a temperature dependence, theforward voltage of the diode fluctuates at low and high temperatures,which causes a risk that determination accuracy of the resistance stateof the phase change element deteriorates. On the other hand, if a supplyvoltage is stepped down, it is possible to generate a voltage at whichthe temperature dependence of the diode is cancelled. However, in theconfiguration example of the Patent Reference 1, the boost voltage VSAapplied to the bit line is drastically decreased when assuming thesupply voltage of about 1 to 1.5V, and therefore voltage margin (sensingmargin) of the read operation of the memory cell cannot be obtained.That is, if the bit line voltage is decreased in a state where the wordline is maintained at the ground potential, the voltage applied to thephase change element becomes small, and it becomes difficult toconfigure the read circuit for detecting the current change. In thismanner, in the conventional phase change memory device having the diodecell structure, there is a problem that the temperature fluctuationcannot be suppressed by cancelling the temperature dependence of thediode while obtaining the margin of the read operation.

SUMMARY

The present invention seeks to solve one or more of the above problemsand provides a semiconductor memory device capable of suppressinginfluence of temperature fluctuation of a diode and obtaining excellentsensing margin in a read operation of a memory cell including a phasechange element and the diode.

In one of aspects of the invention, there is provided a semiconductormemory device comprising: a memory cell including a memory element and adiode which are connected in series between a first line and a secondline; a first voltage generating circuit generating a first voltagehaving no temperature dependence; a second voltage generating circuitgenerating a second voltage lower than the first voltage, the secondvoltage having a temperature dependence opposite to that of a forwardvoltage of the diode; and a control circuit detecting a resistance stateof the memory element in accordance with a change in current flowing inthe memory cell in a state where the first voltage is applied to thefirst line and the second voltage is applied to the second line, in aread operation of the memory cell.

According to the semiconductor memory device of the invention, in theread operation of the memory cell having a diode cell structure, acurrent flows from the first line applied with the first voltage to thesecond line applied with the second voltage through the memory cell, andthe resistance state of the memory element is detected in accordancewith a change in the current. At this point, since the first voltage hasno temperature dependence and the second voltage has a temperaturedependence opposite to that of the diode, it is possible to determinethe resistance state of the memory element in a state where thetemperature dependence of the forward voltage of the diode is cancelled.Thus, in the semiconductor memory device, excellent sensing margin canbe obtained within a wide temperature range and the configuration of thecontrol circuit can be simplified.

For example, the first line may be a bit line and the second line may bea word line. In this case, the first voltage applied to the bit line maybe set to a positive voltage between a supply voltage and a groundpotential, and the second voltage applied to the word line may be set toa negative voltage lower than the ground potential. Further, whenemploying an arrangement including a plurality of memory cells formed atintersections of a plurality of bit lines and a plurality of word lines,the above-mentioned configuration and voltage relation can be applied toeach of the memory cells.

According to the present invention, in the semiconductor memory deviceemploying the diode cell structure in which the memory cell is formedusing the memory element and the diode, when the forward voltage of thediode has the temperature dependence, influence due to temperaturefluctuation in reading the memory cell can be suppressed by giving anopposite temperature dependence to the second voltage. In this case, ifthe second voltage is set to a negative voltage, the first voltage canbe set to a low positive voltage (for example, 0.5V). Therefore, it ispossible to easily configure the control circuit (particularly, the readcircuit) without using a boost voltage used in the conventionalconfiguration.

BRIEF DESCRIPTION OF THE DRAWINGS

The above featured and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram showing a basic configuration of a phase changememory device to which the present invention is applied;

FIG. 2 is a diagram showing an example of general voltage-currentcharacteristics of a phase change element;

FIG. 3 is a diagram showing an example of general voltage-currentcharacteristics of a diode;

FIG. 4 is a diagram showing a specific circuit configuration of a readcircuit;

FIG. 5 is a diagram showing operation waveforms in a read operation ofthe phase change memory device;

FIG. 6 is a diagram showing an equivalent circuit of a current path inthe read operation from the read circuit to a word line through a memorycell to be read;

FIG. 7 is a diagram showing an example of circuit configurations of aVBLP generating circuit and a VKK generating circuit;

FIG. 8 is a diagram showing voltage-temperature characteristics of FIG.6 in the read operation; and

FIG. 9 is a diagram showing voltage-temperature characteristics as acomparison example for the embodiment, corresponding to FIG. 8 in whicha conventional configuration is employed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposes. In the following, theembodiments will be described in which the present invention is appliedto a phase change memory device storing data in a memory cell employingthe diode cell structure.

FIG. 1 is a diagram showing a basic configuration of the phase changememory device to which the present invention is applied. In FIG. 1, amemory cell array 10 includes a large number of memory cells MC arrangedin a matrix, and there are provided a word line decoder 11, a bit linecontrol circuit 12 and a VKK generating circuit 14 around the memorycell array 10. Further, the bit line control circuit 12 includes a bitline decoder 30, a write circuit 31 and a read circuit 32.

In the memory cell array 10, a plurality of the memory cells MC eachemploying the diode cell structure are arranged at intersections of aplurality of bit lines BL (the first lines of the invention) and aplurality of word lines WL (the second lines of the invention). Each ofthe memory cells MC is composed of a phase change element 20 (the memoryelement of the invention) and a diode 21 which are connected in series.One end of the phase change element 20 is connected to the bit line BL,and the cathode of the diode 21 is connected to the word line WL. Thephase change element 20 is made of, for example, chalcogenide phasechange material (for example, Ge, Sb and Te). In a multi-layer structureof the phase change memory device, an electrode located immediatelybelow the phase change element 20 is used as a heater, and the phasechange element 20 is heated by the heater when a write current flows inthe memory cell MC, so that its state can be reversibly changed betweena high-resistance amorphous state and a low-resistance crystallinestate. In addition, positions of the phase change element 20 and thediode 21 can be replaced with each other in the memory cell MC.

The word line decoder 11 decodes an input word line selecting addressADR (W) and drives a word line WL selected among the plurality of wordlines WL according to the decoding result. The VKK generating circuit 14generates a negative voltage VKK to be applied to the selected word lineWL and outputs it to the word line decoder 11. In a read operation ofthe memory cell array 10, the selected word line WL is controlled sothat its level is maintained at the negative voltage VKK, as describedlater. Meanwhile, non-selected word lines WL are controlled to bemaintained at the ground potential VSS. When retaining data in thememory cell array 10, all the word lines WL are maintained at the groundpotential VSS. Moreover, the phase change memory device includes a VBLPgenerating circuit 13 and a reference voltage generating circuit 15which are not shown in FIG. 1. In addition, configuration and operationof the VKK generating circuit 14 and the VBLP generating circuit 13 willbe described later.

The bit line decoder 30 of the bit line control circuit 12 (the controlcircuit of the invention) includes a plurality of switches SW connectedto the plurality of bit lines BL, decodes an input bit line selectingaddress ADR(B), and connects a bit line BL selected according to thedecoding result to a data line DL via each of the switches SW. Forexample, an MOS transistor whose conductivity is controlled by a controlsignal applied to its gate is used as each of the switches SW of the bitline decoder 30. As described above, it is possible to select anarbitrary memory cell MC in the memory cell array 10 by specifying theword line selecting address ADR(W) and the bit line selecting addressADR(B).

The write circuit 31 of the bit line control circuit 12 has a well-knowncircuit configuration and amplifies data inputted through aninput/output signal line IOL so as to send the data to the data line DL,in a write operation of the memory cell array 10. This data is sent fromthe write circuit 31 to the bit line decoder 30 and is written into apredetermined memory cell MC through a bit line BL corresponding to thebit line selecting address ADR(B).

The read circuit 32 of the bit line control circuit 12 receives data,which is readout from the memory cell MC in the read operation, throughthe bit line decoder 30 and the data line DL and amplifies the data soas to send it to the input/output signal line IOL, in the read operationof the memory cell array 10. As shown in FIG. 1, a supply voltage VDDand a ground potential VSS are supplied to the read circuit 32.

Here, characteristics of the phase change element 20 and the diode 21 ofthe memory cell MC will be described with reference to FIGS. 2 and 3.FIG. 2 shows an example of general voltage-current characteristics ofthe phase change element 20. In FIG. 2, there are divided regionsincluding a region Ra in the read operation with a small current, aregion Rb in which the phase change element 20 shifts to thelow-resistance crystalline state in a set write operation, and a regionRc in which the phase change element 20 shifts to the high-resistanceamorphous state in a reset write operation. Further, in the region Ra,there are shown a characteristic Cs in which the phase change element 20is in a low-resistance state and a characteristic Cr in which the phasechange element 20 is in a high-resistance state.

Slopes of two characteristics Cs and Cr in the region Ra correspond toreciprocals of respective resistances. Thus, it is found from FIG. 2that a resistance (reset resistance) of the characteristic Cr having asmall slope is larger than a resistance (set resistance) of thecharacteristic Cs having a large slope. Generally, the phase changeelement 20 maintaining a high reset resistance is defined as logic “0”,and the phase change element 20 maintaining a low set resistance isdefined as logic “1”. For example, the reset resistance is about 1 MΩ,and the set resistance is about 30 kΩ.

In the write operation, the voltage applied to the phase change element20 in the reset state is increased, and when the voltage exceeds athreshold voltage Vth of FIG. 2, a large current suddenly flows, therebyshifting to the region Rb (set writing). Further, when a larger voltageis applied to the phase change element 20, a much larger current flows,thereby shifting to the region Rc (reset writing). In the set writing,the phase change element 20 is gradually heated and shifts to thecrystalline state. In the reset writing, the phase change element 20 ismelted by the heat generated by the much larger current within a shorttime and thereafter is rapidly cooled so as to shift to the amorphousstate. In addition, the threshold voltage Vth varies widely depending onprocess or temperature, and the lower limit of the variation of thethreshold voltage Vth is about 0.6V. Therefore, in consideration ofmargin, the voltage applied to the phase change element 20 in the readoperation is desired to be set to about 0.3V.

FIG. 3 shows an example of general voltage-current characteristics ofthe diode 21. In FIG. 3, the horizontal axis indicates a forward voltageof the diode 21, and the vertical axis indicates logarithmic values ofthe diode current, and a characteristic C1 in the high temperature and acharacteristic C2 the low temperature are compared. Further, a readcurrent Irs during the read operation of the phase change element 20 inthe set state is shown overlapped with the characteristics C1 and C2. Asunderstood from FIG. 3, the high-temperature characteristic C1 and thelow-temperature characteristic C2 are different from each other due tothe temperature dependence of the diode 21, and a voltage value of anintersection between the read current Irs and the low-temperaturecharacteristic C2 (0.98V) is larger than that between the read currentIrs and the high-temperature characteristic C1 (0.88V).

Next, FIG. 4 shows a specific circuit configuration of the read circuit32. The read circuit 32 shown in FIG. 4 includes ten transistors Q1 toQ10 and an inverter 22. Each of transistors Q5, Q6 and Q7 is a PMOS-typetransistor and each of transistors Q1 to Q4, Q8, Q9 and Q10 is anNMOS-type transistor. Among these, a pair of transistors Q6, Q8 and apair of transistors Q7, Q9 form a latch circuit, which latches a signaltransmitted via a node N2 in the read operation and outputs it via anode N1. Anode N3 is connected to the supply voltage VDD via thetransistor Q5, and a node N4 is connected to the ground potential VSSvia the transistor Q10.

The input/output signal line IOL is connected to the node N1 via thetransistor Q1, and the transistor Q1 is controlled in response to anoutput signal SO applied to its gate. Further, the signal at the node N1is connected to a reference signal REF via the transistor Q2. Meanwhile,the data line DL is connected to the node N2 via the transistor Q3, andis connected to a positive voltage VBLP via the transistor Q4 forprecharging. In a precharge operation, the transistor Q4 is controlledin response to a precharge signal PRE applied to its gate. Further, aninverted signal of a sensing signal SS is applied to gates of thetransistors Q2 and Q3 via the inverter 22. In the configuration of theembodiment, since the low positive voltage VBLP is applied to the bitline BL, as different from the conventional configuration (for example,see FIG. 5 of the Patent Reference 1), the read circuit 32 can beoperated by the supply voltage VDD without using an internally boostedsupply voltage.

Next, the read operation of the phase change memory device of theembodiment will be described with reference to FIGS. 5 and 6. FIG. 5shows operation waveforms in the read operation of the phase changememory device. In FIG. 5, operation waveforms of a word line WLs and abit line BL respectively selected corresponding to the memory cell MC tobe read and an operation waveform of the bit line selecting addressADR(B) are shown, and additionally operation waveforms of the prechargesignal PRE, the sensing signal SS, the output signal SO and the node N1respectively in the read circuit 32 of FIG. 4 are shown for comparison.Meanwhile, FIG. 6 shows an equivalent circuit of a current path in theread operation from the read circuit 32 to the word line WLs through thememory cell MC to be read. In FIG. 6, the read circuit 32, the bit lineBLs, the phase change element 20 and the diode 21 of the memory cell MC,and the word line WLs are only illustrated for simplicity. Further, avoltage between both ends of the phase change element 20 is representedas Vg, a voltage between both ends of the diode 21 is represented as Vd,and an intermediate node therebetween is a node N0.

First, the word line WLs and the bit line BLs are in an inactivatedstate at timing T0 as a standby state before the read operation, andboth levels of the word line WLs and the bit line BLs are set to theground potential VSS. In the state of FIG. 6, current dose not flowthrough the current path. Further, the precharge signal PRE, the sensingsignal SS, the output signal SO and the bit line selecting address ADR(B) are also in the inactivated state at the timing T0 and set to a lowlevel (the ground potential VSS) respectively. In addition, the node N1is set to the same level as the reference signal REF by an operation ofthe transistor Q2 and the inverter 22 in FIG. 4.

Next, the word line WLs is selected by the word line decoder 11, andconsequently the level of the word line WLs decreases from the groundpotential VSS to the negative voltage VKK at timing T1. At this point,the precharge signal PRE is changed to a high level (the supply voltageVDD) so that the transistor Q4 turns on, and the positive voltage VBLPis supplied to the data line DL of FIG. 4. Thus, the level of the bitline BLs which is connected to the data line DL via the switch SW of thebit line decoder 30 increases from the ground potential VSS to thepositive voltage VBLP. Meanwhile, non-selected bit lines are maintainedat the ground potential VSS. The positive voltage VBLP is set to, forexample, about VBLP=0.5V for about VDD=1.8V (1.7 to 1.9V). In addition,the activated bit line selecting address ADR (B) is assumed to bechanged to the high level at the timing T1.

Here, in the current path of FIG. 6, the bit line BLs is at the positivevoltage VBLP and the word line WLs is at the negative voltage VKK, andthe diode 21 of the memory cell MC is forward-biased so that the currentflows. The read operation is controlled so that a current correspondingto, for example, about Vg=0.3V flows in the phase change element 20.Then, the current value in the current path varies in accordance withthe resistance state of the phase change element 20, and the logic “0”or “1” stored in the memory cell MC can be determined by detecting thecurrent value. In FIG. 6, the negative voltage VKK is a voltage obtainedby subtracting the voltage applied to the memory cell MC (sum of thevoltages Vg and Vd) from the positive voltage VBLP. That is, thissatisfies the following relation:

VKK=VBLP−(Vg+Vd)

In the embodiment, the value of the negative voltage VKK isappropriately controlled in consideration of the temperature dependenceof the diode 21, and a specific operation thereof will be describedlater.

Subsequently, the precharge signal PRE is changed from the high level tothe low level so that the transistor Q4 turns off at timing T2, andprecharging of the bit line BLs is cancelled. Therefore, the level ofthe bit line BLs gradually changes in accordance with the resistancestate of the phase change element 20 of the selected memory cell MC.Then, as shown in FIG. 5, the bit line BLs decreases to a level lowerthan the reference signal REF when the phase change element 20 is in thelow-resistance state (set state), and the bit line BLs maintains a levelhigher than the reference signal REF when the phase change element 20 isin the high-resistance state (reset state).

Subsequently, when the level of the word line WLs returns from thenegative voltage VKK to the ground potential VSS at timing T3, thesensing signal SS is changed from the low level to the high level.Thereby, in the latch circuit including the transistors Q6 to Q9 of FIG.4, the output level is determined in accordance with the level relationbetween the nodes N1 and N2. That is, as shown in FIG. 5, the node N1changes to the low level (the ground potential VSS) when the level ofthe bit line BLs is higher than that of the reference signal REF, andthe node N1 changes to the high level (the supply voltage VDD) when thelevel of the bit line BLs is lower than that of the reference signalREF.

Subsequently, the output signal SO is changed from the low level to thehigh level at timing T4. Thereby, the transistor Q1 of FIG. 4 turns on,and the signal maintained at the node N1 is outputted to theinput/output signal line IOL via the transistor Q1. Further, at thetiming T4, the bit line selecting address ADR (B) is changed to the lowlevel while remaining in the inactivated state, and the level of the bitline BLs decreases to the ground potential VSS.

Subsequently, the sensing signal SS and the output signal SO are bothchanged from the high level to the low level at timing T5. Thereby, thetransistor Q1 is turned off, and the transistors Q2 and Q3 are turnedon, so that the read operation is completed. At this point, the level atthe node N1 returns to the reference signal REF again.

A feature of the phase change memory device of the embodiment is avoltage control using the negative voltage VKK necessary for driving theword line WL, which will be described in detail below. FIG. 7 shows anexample of circuit configurations of the VBLP generating circuit 13 (thefirst voltage generating circuit of the invention) generating thepositive voltage VBLP (the first voltage of the invention) applied tothe bit line BL and the VKK generating circuit 14 (the second voltagegenerating circuit of the invention) generating the negative voltage VKK(the second voltage of the invention) applied to the word line WL. InFIG. 7, a reference voltage VREF is supplied to the VKK generatingcircuit 14 and the VBLP generating circuit 13 from the reference voltagegenerating circuit 15 having a well-known circuit configuration. Thereference voltage VREF is used as a reference value for the negativevoltage VKK and the positive voltage VBLP and has a constant voltagevalue without the temperature dependence. For example, the referencevoltage VREF is set to about 1V.

The VBLP generating circuit 13 generates the positive voltage VBLP basedon the reference voltage VREF outputted from the reference voltagegenerating circuit 15 and includes resistors R1, R2, a differentialamplifier 50, a transistor Q20 and a capacitor 51. The resistors R1 andR2 connected in series are connected between the reference voltage VREFand the ground, and a voltage VREFa corresponding to the ratio of theresistors R1 and R2 appears at a node N10 between the resistors R1 andR2. For example, when the two resistors R1 and R2 are equal to eachother in a state of VREF=1V, the voltage VREFa becomes 0.5V. The nodeN10 is connected to a minus input terminal of the differential amplifier50. The transistor Q20 is a PMOS-type and has a source connected to thesupply voltage VDD, a drain connected to a plus input terminal (nodeN11) of the differential amplifier 50, and a gate connected to an outputterminal of the differential amplifier 50. The capacitor 51 is connectedbetween the node N11 and the ground, and the positive voltage VBLPhaving the same level as the voltage VREFa is outputted from the nodeN11. As described above, the positive voltage VBLP is maintained at theconstant voltage value without the temperature dependence because it isgenerated based on the reference voltage VREF having no temperaturedependence.

The VKK generating circuit 14 is provided with a VKK determinationcircuit 40, a ring oscillator circuit 41 and a VKK pumping circuit 42.The VKK determination circuit 40 includes resistors R3, R4, a diode 52and a comparator 53. The resistors R3, R4 and the diode 52 are connectedin series and are connected between the reference voltage VREF and anode N14. A node N12 between the resistors R3 and R4 is connected to aplus input terminal of the comparator 53. Here, the diode 52 has thesame characteristics as the diode 21 of the memory cell MC. A minusinput terminal of the comparator 53 is connected to the node N11 andreceives the positive voltage VBPL outputted from the VBLP generatingcircuit 13. The comparator 53 outputs a detection signal of which thelogics I/O change in accordance with the level relation between thevoltage at the node N12 and the positive voltage VBPL.

The ring oscillator circuit 41 includes inverters 54, 56, 57, 58 and aNAND gate 55. The NAND gate 55 receives the detection signal from thecomparator 53 and an output of the inverter 54 respectively, and theinverters 56, 57 and 58 are connected in series in this order to theoutput side of the NAND gate 55. A node N13 at the output side of thefinal stage inverter 58 is fed back to the first stage inverter 54. Thisring-shaped connection allows the ring oscillator circuit 41 to output asquare wave having a predetermined period from the node N13 when thedetection signal from the comparator 53 is the logic “1”.

The VKK pumping circuit 42 includes transistors Q21, Q22, Q23, Q24 and apumping capacitor 59. An output of the ring oscillator circuit 41 isapplied to commonly connected gates of a PMOS type transistor Q21 and anNMOS type transistor Q22, and commonly connected drains thereof areconnected to one end of the pumping capacitor 59. The transistor Q23 isconnected between the other end of the pumping capacitor 59 and theground, and the transistor Q24 is connected between the other end of thepumping capacitor 59 and the node N14. As described above, the cathodeof the diode 52 is connected to the node N14, and the voltage at thenode N14 is outputted as the negative voltage VKK.ee

In the circuit configuration of FIG. 7, if the level at the node N12 ishigher than the level of the positive voltage VBLP, the ring oscillatorcircuit 41 and the VKK pumping circuit 42 are activated so as todecrease the level at the node N14 (VKK), and thereby the level at thenode N12 is decreased through the diode 52 and the resistor R4. Further,if the level at the node N12 becomes lower than the level of thepositive voltage VBLP, the ring oscillator circuit 41 and the VKKpumping circuit 42 are deactivated. That is, the node N12 is maintainedat almost the same level as the positive voltage VBLP (for example,0.5V). The resistors R3 and R4 are adjusted so that a current Ir flowingthrough the resistors R3 and R4 is equal to the current flowing throughthe signal path of FIG. 6 in the set state of the memory cell MC. Theadjustment is, for example, R3=50 kΩ and R4=30 kΩ. On the assumption ofVREF=1.0V and VBLP=0.5V, its voltage difference of 0.5V is applied tothe resistor R3 and a value of the current Ir becomes 10 uA.Accordingly, a voltage Vr of the resistor R4 becomes 0.3V (=10 uA×30kΩ). Further, the voltage Vd becomes a voltage at each intersectionbetween the read current Irs (=10 uA) and the diode characteristics (C1and C2) in FIG. 3. In this manner, the feedback of the negative voltageVKK of FIG. 7 is controlled so that the negative voltage VKK conforms toa voltage value obtained by subtracting a sum of the voltages Vr and Vdcorresponding to the flowing current Ir from the positive voltage VBLP.

Hereinafter, voltage-temperature characteristics of FIG. 6 in the readoperation will be described with reference to FIG. 8. Further, FIG. 9shows voltage-temperature characteristics as a comparison example forthe embodiment, corresponding to FIG. 8, in which a conventionalconfiguration is employed. FIGS. 8 and 9 show graphs representingtemperature dependences of voltages of the memory cell MC within anassumed temperature range (−5 to 110 degrees Celsius).

As shown in FIG. 8, according to the voltage-temperature characteristicsof the embodiment, the positive voltage VBLP applied to the bit line BLhas no temperature dependence and is maintained at a constant value, andthe negative voltage VKK applied to the word line WL gradually increaseswith a rise in temperature. The negative voltage VKK changes from aminimum voltage value V1 to a maximum voltage value V2 within thetemperature range of −5 to 110 degrees Celsius. Meanwhile, as to thenode N0 of FIG. 6, a voltage VN0 s obtained when the phase changeelement 20 maintains the set resistance and a voltage VN0 r obtainedwhen the phase change element 20 maintains the reset resistance bothchange flatly because they have no temperature dependence. That is,since the temperature dependence of the forward voltage Vd of the diode21 is reverse to that of the negative voltage VKK, their changes arecancelled with each other. In addition, the positive voltage VBLP of thebit line BL is higher than the voltage VN0 s at the node N0 in the setstate by the voltage Vg. A specific example of the voltage relation ofFIG. 8 is such that the change of the negative voltage VKK is V1=−0.78Vand V2=−0.68V for a condition of VBLP=0.5V and VSS=0V. Further, thevoltage at the node N0 is VN0 s=0.3V in the set state, and the voltageVN0 r becomes slightly higher than the ground potential VSS in the resetstate so that the voltage Vg becomes 0.3V.

On the other hand, according to the voltage-temperature characteristicsof the conventional configuration as shown in FIG. 9, although the wordline WL is maintained at the ground potential VSS having no temperaturedependence, the potential of the bit line BL supplied with a boostvoltage has the temperature dependence. That is, both the voltage VN0 sin a case where the phase change element 20 maintains the set resistanceand the voltage VN0 r in a case where the phase change element 20maintains the reset resistance have the same temperature dependence asthe forward voltage Vd of the diode 21, and the potential of the bitline BL changes in conjunction therewith. Within the temperature rangefrom −5 to 110 degrees Celsius, the voltage VN0 s changes from themaximum voltage value Vb to the minimum voltage value Va, while thepotential of the bit line BL higher than the voltage VN0 s by thevoltage Vg changes from the maximum voltage value VBb to the minimumvoltage value VBa. A specific example of the voltage relation of FIG. 9is Va=0.88, Vb=0.98V, VBa=1.18V, VBb=1.28V and Vg=0.3V corresponding tothe characteristics of the diode 21 in FIG. 3.

It is apparent by comparing FIGS. 8 and 9 that, in the embodiment, thenegative voltage VKK lower than the ground potential VSS is supplied tothe word line WL, the low positive voltage VBLP (for example, 0.5V) canbe supplied to the bit line BL. Further, since the negative voltage VKKis controlled to have the temperature dependence opposite to that of thediode 21, it is possible to control so that the read operation of thememory cell MC cannot be affected by the temperature fluctuation. In theconventional configuration, since the voltage applied to the bit line BLis forced to be high, the read operation of the memory cell MC isinevitably affected by the temperature fluctuation, and even if a methodfor controlling the voltage of the bit line BL in accordance with thetemperature, determination accuracy is deteriorated due to variation ofoperating points in the read circuit 32. Accordingly, in the embodiment,it is possible to improve sensing margin of the memory cell MC withoutbeing affected by the temperature fluctuation in comparison with theconventional configuration. On the other hand, in the conventionalconfiguration, in order to achieve a higher-speed read operation, it isnecessary to maintain the word line WL at a high voltage and to maintainthe bit line BL at the ground potential VSS in a data retentionoperation (in standby). Thereby, the diode 21 is reverse-biased so as togenerate standby leak due to the leak in the diode 21. In contrast, inthe embodiment, it is possible to maintain both the word line WL and thebit line BL at the ground potential VSS in the data retention operation(in standby), and the diode 21 is not reverse-biased so that thegeneration of the standby leak can be prevented.

Further, as apparent from FIGS. 8 and 3, in the read operation, it isnot necessary to change voltages of non-selected word lines andnon-selected bit lines from the ground potential VSS as the same as inthe data retention operation (in standby). A current smaller than thediode current for which the diode forward voltage in the graph of FIG. 3is 0.5V flows in each of non-selected memory cells (corresponding tonon-selected word lines at the ground potential VSS) connected to theselected bit line (to which the positive voltage VBLP of 0.5V isapplied), which is sufficiently lower than the read current Irs of thephase change element 20 in the set state, so as almost not to affect thedetermination of the resistance value of the selected memory cell.Further, the voltage applied to each of non-selected memory cells(corresponding to non-selected bit lines at the ground potential VSS)connected to the selected word line (to which the negative voltage VKKis applied) is V1=−0.78V in the low temperature and is V2=−0.68V in thehigh temperature. However, the diode current is sufficiently small whenthe forward voltage of the diode 21 in the graph of FIG. 3 is V1 or V2in the low or high temperature, and there is not a large increase inconsumption current. Accordingly, the read operation can be performed athigh speed from a data retention state (in standby), and consumptioncurrent due to charge/discharge of the non-selected bit lines and thenon-selected word lines is not generated.

Further, in the conventional configuration, since the boost voltageapplied to the bit line BL includes ripple noise larger than that of thepositive voltage VBLP, there is a problem that the resistance state ofthe phase change element 20 cannot be accurately detected when the readcircuit 32 is driven by the boost voltage. In contrast, in theembodiment, since the read circuit 32 can be driven by the supplyvoltage VDD, it is possible to accurately detect the resistance state ofthe phase change element 20. Further, in the conventional configuration,the read circuit 32 driven by the boost voltage needs to be configuredusing thick film transistors each having a thick gate oxide film.Correspondingly, a layout area is enlarged, and fluctuation of thethreshold voltage increases so that the detection accuracy of the readcircuit 32 is deteriorated. In contrast, in the embodiment, the readcircuit 32 configured using thin film transistors each having a thingate oxide film can be achieved so that the detection accuracy can bekept excellent.

In the foregoing, contents of the invention have been specificallydescribed based on the embodiments. However, the present invention isnot limited to the above described embodiments, and can variously bemodified without departing the essentials of the present invention. Forexample, various configurations can be employed for the bit line controlcircuit 12, the VBLP generating circuit 13 and the VKK generatingcircuit 14 without being limited to the configurations of theembodiment, as long as the same purpose can be achieved. Further,semiconductor devices in which the phase change memory device of theinvention can be implemented can include SOC (System on Chip), MCP(Multi chip package), POP (Package on Package) and the like. Further,the present invention is not limited to the phase change memory deviceand can be widely applied to a semiconductor memory device employing thediode matrix cell structure, such as a resistive random access memory(RRAM).

1-14. (canceled)
 15. A device comprising: a memory cell including a resistive memory element and a first diode that are connected in series between a first line and a second line; a first circuit generating a first voltage to be supplied to the first line; a second circuit generating a second voltage to be supplied to the second line, and the second circuit including a second diode.
 16. The device as claimed in claim 15, wherein the second voltage has temperature dependence opposite to that of a forward voltage of the first diode.
 17. The device as claimed in claim 16, wherein the first voltage has no temperature dependence.
 18. The device as claimed in claim 15, further comprising: a memory array comprising a plurality of the memory cells, a plurality of bit lines including the first line, and a plurality of word lines including the second line, each of the memory cells being associated with one of the bit lines and one of the word lines.
 19. The device as claimed in claim 18, wherein, in a read operation of the memory cell, the first voltage is applied to a selected one of the bit lines, the second voltage is applied to a selected one of the word lines, and the ground potential is applied to the other of the bit lines and the other of the word lines.
 20. The device as claimed in claim 18, wherein, in a standby state of the memory cell, a ground potential is applied to at least ones of the bit lines and the word lines.
 21. The device as claimed in claim 15, wherein the first and second voltages are generated in a read operation of the memory cell.
 22. The device as claimed in claim 15, wherein the first voltage is higher than the second voltage.
 23. The device as claimed in claim 22, wherein the first voltage is higher than a ground potential and the second voltage is lower than the ground potential.
 24. The device as claimed in claim 15, wherein the second circuit further including, a resistor connected to the second diode to generate the second voltage.
 25. The device as claimed in claim 24, wherein the second circuit further including, a comparator including a first and second input nodes, the first input node receiving a first reference voltage, the second input node each coupled to the resistor and an additional resistor receiving a second reference voltage, and the comparator including an output node.
 26. The device as claimed in claim 25, wherein the first input node receives the first voltage.
 27. The device as claimed in claim 25, wherein the second circuit further including, a ring oscillator circuit coupled to the output node of the comparator and including an output node; a pumping circuit coupled to the output node of the ring oscillator circuit and outputting the second voltage.
 28. The device as claimed in claim 15, further comprising: a first reference line supplying a first reference voltage to the first circuit; a second reference line supplying a second reference voltage to the second circuit.
 29. The device as claimed in claim 28, further comprising: a connection line connecting an output node of the first circuit to the second circuit to supply the first voltage to the second circuit.
 30. The device as claimed in claim 29, wherein the second circuit generates the second voltage in response to the first voltage supplied from the first circuit and the second reference voltage.
 31. The device as claimed in claim 15, wherein the first circuit is supplied with a first reference voltage to generate the first voltage, the first voltage relating the first reference voltage.
 32. The device as claimed in claim 31, wherein the first reference voltage has no temperature dependence.
 33. The device as claimed in claim 15, wherein the second diode of the second circuit has the substantially same in characteristics as the first diode of the memory cell.
 34. The device as claimed in claim 15, further comprising: a sensing circuit coupled to the second line and sensing a resistance state of the resistive memory element in accordance with a current flowing the second line.
 35. The device as claimed in claim 15, wherein the second diode of the second circuit corresponds to the first diode of the memory cell to generate the second voltage.
 36. A method comprising: performing a first operation on a memory cell including a resistive memory element and a first diode that are associated with a bit line and a word line; the performing comprising, applying a first voltage to one of the bit line and the word line, generating a second voltage by using a voltage generating circuit including a second diode, and applying the second voltage to the other of the bit line and the word line.
 37. The method as claimed in claim 36, wherein the first operation is a read operation to read data from the memory cell.
 38. The method as claimed in claim 36, wherein the performing further comprises, changing the second voltage from a first level to a second level that is higher than the first level when a voltage of a first terminal inserted between the resistive memory element and the first diode changes from a first value to a second value that is lower than the first value, changing the second voltage from the first level to a third level that is lower than the first level when a voltage value of the first terminal changes from the first value to a third value that is higher than the first value.
 39. The method as claimed in claim 36, wherein the second diode of the voltage generating circuit corresponds to the first diode of the memory cell. 